This invention relates to voltage generator circuitry and, in particular, to sense amplifier latch voltage waveform generator circuits.
Many of today's n-channel field effect transistor dynamic random access memories use a sense amplifier having a cross-coupled pair of transistors with the sources being coupled to the drain of a latch transistor. A generator circuit producing a latch voltage waveform is connected to the gate of the latch transistor. The generator circuit used generally consists of a plurality of parallel field effect transistors of ever-decreasing resistance with separate delay elements connecting the respective gate terminals. A voltage latch waveform (an enabling signal), applied to the gate of the first of the parallel transistors, turns on the first transistor and then thereafter, at selected time intervals, turns on each of the next of the plurality of parallel transistors. As each of the parallel transistors turns on, the output potential of the generator circuit changes to bias the latch transistor more heavily on. One problem with this type of generator circuit is that the response time is slower than is desired in some applications. Another problem is that the slope of the produced voltage waveform increases essentially in steps as each of the parallel transistors turns on and is not essentially ever-increasing after a threshold voltage is reached. Still another problem is that the generator circuits are moderately complex and require more silicon area for implementation than is desirable in some applications.
It is desirable to have a sense amplifier latch voltage waveform generator circuit which produces an output voltage waveform that has essentially an ever-increasing slope over a useful voltage range after a threshold potential level is reached and which can be implemented in a relatively moderate area of silicon.